VATAGP3_1 Specifications (preliminary) V0.94 December 2004 Ideas ASA, Veritasveien 9, Box 315, N-1323 Høvik, Norway Phone: +47 67 81 65 00, Fax: +47 67 81 65 01, E-mail: ideas@ideas.no, homepage: http://www.ideas.no Bank: Kreditkassen, Account no: 6094.05.51881, Swift: XIAN NO KK, Enterprise Number: NO 96 56 50 776 VATAGP3_1 General Table of Contents General ..........................................................................................................................................3 Physical..........................................................................................................................................3 Electrical........................................................................................................................................4 Pad Description .............................................................................................................................5 Layout............................................................................................................................................8 Functional description .................................................................................................................10 6.1 Using VATAGP3_1 in parallel..............................................................................................10 6.2 Current compensation ............................................................................................................11 6.3 Biasing ...................................................................................................................................12 6.4 Control register ......................................................................................................................13 6.5 ASIC test and calibration .......................................................................................................14 6.6 Threshold DACs ....................................................................................................................14 7 Readout modes ............................................................................................................................15 a) Mode 1: Serial readout ...........................................................................................................15 7.1 Mode 2: Sparse readout..........................................................................................................16 7.2 Mode 3: Sparse readout with neighbour channels .................................................................18 7.3 Mode 4: Random Access Read-out (RAR) with neighbour channels...................................20 1 2 3 4 5 6 Page 2 of 21 Ideas ASA General VATAGP3_1 1 General The VATAGP3_1 is a 128-channel “general purpose” charge sensitive amplifier. Each channel features low-noise/low-power buffered preamplifiers, a shaper with sample/hold, multiplexed analogue readout and calibration facilities. In addition, each channel has a fast shaper that gives a trigger signal. The analogue value and the address of the trigging channels are read out with a flexible serial read-out (VA-style), sparse read-out system, sparse read-out with neighbours or read-out of any desired channel, the Random-Access Read-out (RAR). The VATAGP3_1 also offers input leakage current compensation automatically adjusted in each preamplifier channel. The VATAGP3_1 is designed for use in systems employing many chips in parallel, sharing some control lines and all output lines with the other modules. 2 Physical Process: Die size: 0.8 µm N-well CMOS, double poly, double metal. 10660 µm x 6120 µm(including scribe) Thickness: ~ 600 µm Pad size: Pad pitch: Single row. Pad size: Pad pitch: Pad size: 90 µm x 50 µm 91.2 µm (see Figure 3) 90 µm x 90 µm 140 µm (see Figure 2) 90 µm x 200 µm Input bonding pads: Control, output, and biasing pads: Analogue Power pads: Ideas ASA Page 3 of 21 VATAGP3_1 Electrical 3 Electrical (Simulated values, to be verified by measurements) Power rails: VDD = +2 V, VSS = -2 V, GND = 0 V. Each with separate connections for analogue (AVDD, AVSS and AGND) and digital sections (DVDD, DVSS and DGND) of the chip. Connect to AVSS (-2V) DVDD DVSS DGND AVDD AVSS AGND Nominal values 500 µA all other biases are internally generated and can be unconnected 300 mW (2.3 mW/channel)?? ∼3 mA? ∼6 mA? 0 mA ∼50 mA? ∼100 mA? ∼50 mA? Back contact: Current description: (Quiescent, typical values with mbias=500 µA) Input bias currents: mbias Power dissipation: (Typical values) Quiescent: Gain: DNR: Peaking time, slow shaper Peaking time, fast shaper ~ 44 µA/fC (differential branches added). ~ +18 fC ~ 4 µs ~ 150 ns Page 4 of 21 Ideas ASA Pad Description VATAGP3_1 4 Pad Description Bias pads which do not require bonding (internally generated or pull-up/pull-down) can be bonded for external decoupling, adjustment or forcing. Pads described clock-wise from upper left to lower left (excluding input pads). Positive current direction into the chip. Pad-row on the ASIC top side: Pad name Type Description ai0-6 di Address in, single-ended digital current signal shift_in_d di Shift-register input (downwards) shift_out_u do Shift-register output (upwards) vi ldi Veto input (pos. phase) vib ldi Veto input (neg. phase) regin di Data input for control register Nominal value Current (100 µA) logical Logical low v. logical (pd) low v. logical (pu) logical (pd) Pad-row on the ASIC right side: Pad name Type Description Nominal value AGND p Signal ground for the analogue part 0V DGND p Connect to AGND 0V DVDD p Digital VDD 2V DVSS p Digital VSS -2 V clkin di Clock for control register Logical sh ldi Sample and hold (pos. phase) low v. logical shb ldi Sample and hold (neg. phase) low v. logical res ldi Reset of the readout logic (pos. low v. logical (pd) phase) resb ldi Reset of the readout logic (neg. low v. logical (pu) phase) shiftreg ldi Readout mode (pos. phase) low v. logical (pu) shiftregb ldi Readout mode (neg. phase) low v. logical (pd) gckb ldi Clock for readout (neg. phase) low v. logical gck ldi Clock for readout (pos. phase) low v. logical addr0-6 do Digital output of hit channel Current (100 µA) address addr7-10 do Digital output of chip address Current (100 µA) ioref ai Current sink for the address output Connect to ~0V buffer mgo ao Multi-hit trigger output Current to do Trigger out (positive phase), ~ -1.3 mA referred to DVDD tob do Trigger out (negative phase), ~ 1.3 mA referred to DVSS vthrh ai High threshold for the discriminator 2V? vfsf ai Control voltage for the feedback 200 mV (int. gen.) resistor (NMOS) in the fast shaper Ideas ASA Page 5 of 21 VATAGP3_1 Pad Description vfss vfp outm_u outp_u outm_d outp_d vthr cali cale mbias AVSS_CC AVDD AVSS ai ai ao ao ao ao ai ai ai ai ai p p Control voltage for the feedback resistor (NMOS) in the slow shaper Control voltage for the feedback resistor (NMOS) in the preamplifier Diff. analogue output, neg. phase (upwards shift-register) Diff. analogue output, pos. phase (upwards shift-register) Diff. analogue output, neg. phase (downwards shift-register) Diff. analogue output, pos. phase (downwards shift-register) Normal threshold for the discriminator Test pulse with internal capacitor Test pulse with external capacitor Bias reference for all the internally generated biases Reference for current compensation analogue VDD analogue VSS 150 mV (int. gen.) -300 mV (int. gen.) 0-200 µA 0-200 µA 0-200 µA 0-200 µA ⇑ 50 mV? voltage step charge 500 µA –2V 2V -2 V Pad-row on the ASIC bottom side: Pad name Type Description regout do Data output of the control register vob ldo Veto output (neg. phase) vo ldo Veto output (pos. phase) shift_in_u di Shift-register input (upwards) shift_out_d do Shift-register output (downwards) ai6-0 di Address in, single-ended digital current signal Nominal value logical low v. logical low v. logical logical logical Current (100 µA) Inner control pad row, from upper to lower: Pad name Type Description dlt ldi Inhibit further trigger generation, pos. phase dltb ldi Inhibit further trigger generation, neg. phase cs ldi Chip select (to select a specific chip for RAR read-out), pos. phase csb ldi Chip select (to select a specific chip for RAR read-out) , neg. phase Nominal value Coordinates Internally pulled 9854 / 5061.8 low Internally pulled 9854 / 4921.8 high Internally pulled 9854 / 4781.8 low Internally pulled high 9854 / 4641.8 Page 6 of 21 Ideas ASA Pad Description VATAGP3_1 Pads on the second pad-row, listed from upper to lower. These pads are for over-riding of internally generated biases. Pad name slewb obi mo_bi vref Type ai ai ai ao/ai Description Bias for the slew rate limitation circuit Bias for the discriminators Bias for the address and mgo current sources. Reference for the output buffer, internally generated by a dummy slow shaper Trigger width bias Bias for the fast shaper Control voltage for HP -filter resistor (NMOS) in front of discriminator. Possible to change with the global control bit vrcn_sel. Bias for the preamplifiers Bias for the slow shaper Bias for the analog output buffer Bias for threshold DACs Nominal value -6 µA (int. gen.) 90 µA (int. gen.) -140 µA(int.gen.) ~ -600 mV Coordinates 9877.8 / 2904 9877.8 / 2764 9877.8 / 2624 9877.8 / 2484 trigwb shabf vrc ai ai ai preb shabs ibuf ref_bias ai ai ai ai -12 µA (int. gen.) 65 µA (int. gen.) Vrcn_sel = 0: 1.4 V Vrcn_sel = 1: 1.2V 500 µA (int. gen.) 22 µA (int. gen.) 220 µA (int. gen.) 20 µA (int. gen.) 9877.8 / 2344 9877.8 / 2204 9877.8 / 2064 9877.8 / 1924 9877.8 / 1784 9877.8 / 1644 9877.8 / 1504 p = power, di = digital in, do = digital out, ldi= low voltage differential digital in, ldo= low voltage differential digital out, ai=analogue in, ao = analogue out, pu = pull-up, pd = pull-down Low voltage logical = 0V(“1”)/-0.2V(“0”) Logical = +2V (“1”) / -2V (“0”) Ideas ASA Page 7 of 21 VATAGP3_1 Layout 5 Layout [dlt, dltb, cs and csb pads] [Redundant analogue GND pads (Connect for lower GND line series resistance)] [Pads for overriding of biases] Figure 1: Chip plot of the VaTagp3_1 Page 8 of 21 Ideas ASA Layout VATAGP3_1 B A (I127) = 72.8 / 99.8 B (I0) = 242.8 / 5891.0 C (ai0) = 8450.8 / 5656.0 D (regin) = 9990.8 / 5656.0 E (agnd) = 10363.2 / 5938.4 F (dgnd) = 10473.2 / 5658.4 G (avss_cc) = 10473.2 / 338.4 H (avss) = 10363.2 / 58.4 I (regout) = 9990.8 / 433.2 J (ai0) = 8450.8 / 433.2 K (edge) = 0 / 0 C D E F A J I H G K Figure 2: Chip geometry & pad placement (Not to scale - all dimensions in µm. Please note that the referred co-ordinates are layout co-ordinates. Add 50-100 µm on each side for scribe/cutting tolerances). 170µm 91.2µ 50µm 90µm Figure 3: Definition of input pad size and pitch. Ideas ASA Page 9 of 21 VATAGP3_1 Functional description 6 Functional description HPfilter H2(s) Semigaussian “fast” shaper H3(s) Levelsensitive Discriminator H1(s) Semigaussian Charge Integrator “slow” shaper (preamp) S/H vthr (See the following text for more detailed information) 6.1 Using VATAGP3_1 in parallel The VATAGP3_1 is designed to be used in parallel for reading out a large number of channels. There are 4 bits for the chip address, giving a maximum of 16 chips on the same bus, with a total of 2048 channels. The pads are placed so that signals that go from one chip to the next are on the opposite side, making the PCB routing easy. The signals should be connected this way: (chip number in parenthesis) vo(1) to vi(2) vob(1) to vib(2) shift_out_u(1) to shift_in_u(0) shift_out_d(1) to shift_in_d(2) regout(1) to regin(2) All other control signals shall be in parallel. Page 10 of 21 Readout logic (serial and/or sparse) Monostable (fixed width) Trigger Out Ideas ASA Functional description VATAGP3_1 6.2 Current compensation VATAGP3_1 uses an active current compensation by introducing a MOS source/sink at the preamplifier’s input. The MOS device is controlled by a slow differential amplifier, which senses the voltage difference between the input and the output nodes of the preamp. The control signal nside can be used to set the current compensation to source- or sink-modus depending on which side of the detector the leakage current originates. The figure below shows the concept of this scheme. Detector +Vbias Ileak+ Va1 prime2 bias vfp low-power diff-amp to shaper Ileak-Vbias preamplifier Avss c Simplified schematic showing the principle of the current compensation used in the Va3Tta. The switches are controlled by nside. There is also a separate switch controlled by the bit cc_on for turning the current compensation off (not shown). Ideas ASA Page 11 of 21 VATAGP3_1 Functional description 6.3 Biasing The VATAGP3_1 is designed to have only one external bias: mbias. All other biases are internally generated, where most biases are a fraction of mbias. However, sometimes it is necessary to adjust or force the biases to other values than the nominal. Pads are available for all biases so that external adjustment is possible. Generation of bias currents/voltages Figure shows a possible approach for generating the necessary bias currents and voltages. mbias is a current into the chip (resistor to VDD). VDD VDD VFP (VFSS) VSS mbias (shabs/ shabf) = I/O pad Figure 4: Bias current and voltage generation Decoupling of power and bias lines It is recommended to decouple the power lines to GND. Decoupling recommendations for bias lines varies, but most of the biases (including mbias) should be decoupled to AVSS. Use 100 nF ceramic capacitors on the power lines as close as possible to each chip and 1-100 uF tantalum capacitors common for all chips on a PCB. Use 100 nF on the mbias (and eventually other biases that are externally generated) close to the chip. Page 12 of 21 Ideas ASA Functional description VATAGP3_1 6.4 Control register The VATAGP3_1 has a 649 bit long control register, set by regin and clkin. Bit 1) 1 Name cc_enable Function Enable current compensation Current compensation network set for connection to n-side of the detector. Test mode on Select signal polarity Selects internal bias generation for the Vrc bias. Set low for positive input signals and high for negative signals. chip address Disable channel (assumed that vthrh = +2V/-2V) 2 n_side 3 4 5 test_on select Vrcn_sel 6:9 10:137 138:521 522:649 addr[10:7] Threshold Norm/High for ch[0:127] DAC[2:0] for ch[0:127] test_enable for ch[0:127] Threshold DACs Enable injection of calpulse into channel 1) Bit number in the control register. Bit 1 is the first bit after regin, bit 649 is the last bit before regout. Reverse the order when downloading the bit-stream (download bit 649 first and bit 1 last). Ideas ASA Page 13 of 21 VATAGP3_1 Functional description 6.5 ASIC test and calibration Each channel can be individually tested. This function is enabled by setting bit test_on in the control register to “1”. The test_enable mask must have one of it’s bits set to “1” which will select the corresponding channel (selecting more than one channel is possible due to AC coupling on the inputs but is not expected to be very useful). The channel(s) that has been selected will be sensitive to test-signals injected at the cale/cali inputs. Connect either the cali or the cale signal. When using the cale signal, place the 1.8 pF capacitor very close to the chip to prevent pickup. When using the cali signal, there is a ~1.0 pF capacitor internally in the chip. A voltage step of 10 mV on the 1.8 pF capacitor gives an input signal charge of 18 fC (~5 MIP). 4k7 47R 4k7 VSS 1.8 pF cale ~1.0 pF cali PCB VATAGP 47R VSS 6.6 Threshold DACs The DACs have nominally 3 mV step size. The step size can be changed by forcing a different ref_bi. The step size in [mV] is ref_bias[µ A]*0.15. DAC0 DAC1 DAC2 Threshold adjust (ref_bias = 20µ A) 0 mV -3 mV -6 mV -9 mV 0 mV 3 mV 6 mV 9 mV 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Page 14 of 21 Ideas ASA Readout modes VATAGP3_1 7 Readout modes The VATAGP3_1 has three different readout modes. After the physics event, each preamplifier will integrate its eventual signal. The slow shaper will shape the signal with a shaping time of 4 us, and the fast shaper with a shaping time of 150 ns. If the signal of the fast shaper has a value larger than the external threshold (vthr or vthr_h), a trigger on the to/tob and mgo lines occur. When the slow shaper reaches the signal peak (nominally after 4 us), the external hold signal (sh/shb) should be applied to sample the peak value. Immediately after this, the readout can start. a) Mode 1: Serial readout Readout is similar to the VA+TA type of ASICs from Ideas. A shift-register will enable readout of one channel at a time. The readout starts with clocking one bit into the first channel of the shift-register with the shift_in_d and gck/gckb signals. See Figure 4 for an example of the timing in this mode. The logic part of the chip can be reset either by applying the res/resb, or by running through the full read-out sequence (more than 128 clocks) so that the last shift bit is clocked out of the register. On power-up, a reset signal should be applied to reset the internal registers/latches with a pulse (~1us- 1ms) on the res/resb lines. Eventually, a number of clocks exceeding the number of channels will set the shift-register to zero. In this mode, the following input signals are not in use and can be left unconnected: shift_in_u shift_out_u shiftreg shiftregb vi vib dlt dltb vo (internal pull down) (internal pull up) (internal pull down) (internal pull down) (internal pull up) (internal pull down) (internal pull up) vob Ideas ASA Page 15 of 21 VATAGP3_1 Readout modes Figure 4: Serial readout a) Physics events happen almost simultaneously in channel 1 and 124. Since the signal is larger than the threshold, a trigger (mgo, ta/tb) is generated. The fast shaper for the trigger logic has a shaping time of 150 ns, which means that dependent of the signal amplitude and the threshold vthr, the trigger can be delayed up to 150 ns. b) Another physics event happen some time later in channel 100. This event also generates a trigger. c) After 4 us, the sample-and-hold signal sh/shb goes high. The signal in channel 1 and 124 has reached the peak, while channel 100 has not fully reached the peak yet. d) A shift bit is clocked into the shift-register by shift_in_d and gck/gckb. The analogue value of channel 0 is enabled at outp_d/outm_d. For each clock (gck/gckb), the shiftbit is clocked to the next channel. e) The last channel is enabled. The shift_out_d goes high to give a shift_in for the next chip in the chain. f) A reset is applied to reset the shift-register. This is not necessary if all channels have been clocked, so that the shift bit has been clocked out of the chip. 7.1 Mode 2: Sparse readout In this readout mode, only the channels with a trigger (signal above the threshold) will be read out to increase the readout speed. As in serial readout, the hold signal sh/shb must be applied 4 us after the trigger. All channels with a trigger will get a read tag. By clocking once with the gck/gckb, the analogue value and the address of the first channel with a tag will be available on the output. After the next clock of gck/gckb, the next channel with a tag will be available. The vo signal goes low when all channels with triggers are read out. If the chip shall be reset before all channels are read out, apply the res/resb signal. Page 16 of 21 Ideas ASA Readout modes VATAGP3_1 In this mode, the following input signals are not in use and can be left unconnected: shift_in_u shift_out_u shift_in_d shift_out_d (internal pull down) (internal pull down) These signals have a fixed level: vi (chip 0) vib (chip 0) shiftreg shiftregb connect to VSS (logic low) connect to VDD (logic high) connect to VSS (logic low) connect to VDD (logic high) dlt/dltb can optionally be used. If they are not used, no connection to these pads is necessary. Figure 5: Sparse readout a) Physics events happen almost simultaneously in channel 1 and 124. Since the signal is larger than the threshold, a trigger (mgo, ta/tb) is generated. The fast shaper for the trigger logic has a shaping time of 150 ns, which means that dependent of the signal amplitude and the threshold, the trigger can be delayed up to 150 ns. b) The disable_late_trigger dlt is applied. This will discard all triggers after this moment. Another physics event happen some time later in channel 100. No trigger is given because dlt is high. Ideas ASA Page 17 of 21 VATAGP3_1 Readout modes c) After 4 us, the sample-and-hold signal sh/shb goes high. The signal in channel 1 and 124 has reached the peak and are held. d) The gck/gckb clocks once. Since veto in vi from the previous chip in the chain is high, no action is taken. e) The gck/gckb clocks once. Veto in vi is low, and the first channel with a hit is enabled at the output together with its address. f) The next and last channel with a hit is enabled at the output together with its address. Veto out vo goes low to indicate that all channels are read out and enable readout of the next chip in the chain. g) Sh and dlt goes low. A reset is applied to reset the shift-register by a pulse on res/resb. This is not necessary if all hit channels have been clocked, so that the veto out in the last chip has gone low. 7.2 Mode 3: Sparse readout with neighbour channels This mode is equal to the sparse readout, except that the neighbours of the channel(s) with trigger can also be read out. As in serial readout, the hold signal sh/shb must be applied 4 us after the trigger. All channels that trigger will get a read tag. By clocking once with the gck/gckb and with shiftreg low, the analogue value and the address of the first channel with a tag will be available on the output. By setting shiftreg high and clocking more clocks, the neighbours of the trigger channel will be available. Be setting shiftreg low and giving another clock of gck/gckb, the next channel with a trigger will be available. All channels with triggers are read out when the vo goes low. If the chip shall be reset before all channels are read out, apply the res/resb signal. These signals have a fixed level: vi (chip 0) vib (chip 0) connect to VSS (logic low) connect to VDD (logic high) dlt/dltb can optionally be used. If they are not used, no connection to these pads is necessary. Page 18 of 21 Ideas ASA Readout modes VATAGP3_1 Figure 6: Sparse readout with neighbour channels a) Physics events happen almost simultaneously in channel 1 and 124. Since the signal is larger than the threshold, a trigger (mgo, ta/tb) is generated. The fast shaper for the trigger logic has a shaping time of 150 ns, which means that dependent of the signal amplitude and the threshold, the trigger can be delayed up to 150 ns. b) The disable_late_trigger dlt is applied. This will discard all triggers after this moment. c) Another physics event happen some time later in channel 100. No trigger is given because dlt is high. d) After 4 us, the sample-and-hold signal sh/shb goes high. The signal in channel 1 and 124 has reached the peak and are held. e) The gck/gckb clocks once. Since veto in vi from the previous chip in the chain is high, no action is taken. f) The gck/gckb clocks once with shiftreg = low. Veto in vi is low, and the first channel with a hit is enabled at the output together with its address. g) The gck/gckb clocks once with shiftreg = high. The analogue values of the two next neighbour channels of the hit channel are read out on the outp_u/outm_u and outp_d/outm_d lines. h) Same as g) i) Same as g) j) The gck/gckb clocks with shiftreg = low. The next channel with a hit is enabled at the output together with its address. k) Same as g) Ideas ASA Page 19 of 21 VATAGP3_1 Readout modes l) Same as g) m) Same as g) n) The chip is reset by setting sh and dlt low and by giving a short res/resb pulse. Dlt is not available on this ASIC. 7.3 Mode 4: Random Access Read-out (RAR) with neighbour channels In this mode, any desired channel can be read out (Random Access Read-out). A typical use of the RAR mode would be a read-out that first reads all triggered channels (mode 2), or primary channels. From the address of the primary channels, one can determine the address of their neighbours. By switching to RAR mode, the neighbouring channels can be read out, e.g. to identify charge sharing or for common mode subtraction. The hold signal sh/shb should be active during the read-out. To set a particular ASIC in RAR-mode, the CS/CSB signals should be active. This enables the address input pins ai0-ai6. The channel to be read out is selected by setting the according channel address on the address input bus. This address is clocked into the ASIC by clocking once with the gck/gckb and with shiftreg low. The analogue value and the address of the channel will be available on the output. This sequence can be repeated to read out any desired number of channels. By setting shiftreg high and CS/CSB low and clocking more clocks, the neighbours of the last channel read out in RAR mode will be available. These signals have a fixed level: vi (chip 0) vib (chip 0) connect to VSS (logic low) connect to VDD (logic high) dlt/dltb can optionally be used. If they are not used, no connection to these pads are necessary. An example read-out sequence using RAR mode and mode 2 can be: a. Physics events happen almost simultaneously in channel 1 and 124. Since the signal is larger than the threshold, a trigger (mgo, ta/tb) is generated. The fast shaper for the trigger logic has a shaping time of 40 ns, which means that dependent of the signal amplitude and the threshold, the trigger can be delayed up to 40 ns. b. The disable_late_trigger dlt is applied. This will discard all triggers after this moment. c. Another physics event happen some time later in channel 100. No trigger is given because dlt is high. d. After 250 ns, the sample-and-hold signal sh/shb goes high. The signal in channel 1 and 124 have reached the peak and are held. Page 20 of 21 Ideas ASA Readout modes VATAGP3_1 e. The gck/gckb clocks once. Since veto in vi from the previous chip in the chain is high, no action is taken. f. The gck/gckb clocks once with shiftreg = low. Veto in vi is low, and the first channel with a hit, channel 1, is enabled at the output together with its address. g. The gck/gckb clocks once with cs/csb active, and the address of channel 4 is applied to the address input buss ai0 – ai6. shiftreg = low. The analog value of channel 4 appears on the analogue output. h. The gck/gckb clocks once with shiftreg = high. The analogue value of the two neighbour channels of channel 4 (channel 3 and 5) becomes available on the outp_u/outm_u and outp_d/outm_d lines. i. The chip is reset by setting sh and dlt low and by giving a short res/resb pulse. The information in this catalogue is subject to change without prior notice. Information given by Ideas ASA is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omission. Ideas ASA Page 21 of 21